The present invention relates to plasma screens and more specifically to the control of cells of a plasma screen.
1. Field of the Invention
A plasma screen is an array type of screen, formed of cells arranged at the intersections of lines and columns, a cell includes a cavity filled with a rare gas, and at least two control electrodes. To create a light point on the screen by using a given cell, the cell is selected by applying a potential difference between its control electrodes, after which the cell gas is ionized, generally by means of a third control electrode. This ionization goes along with an emission of ultraviolet rays. The creation of the light point is obtained by excitation of a red, green, or blue luminescent material by the ultraviolet rays.
2. Discussion of the Related Art
FIG. 1 shows a conventional structure of a plasma screen formed of cells 2. Each cell 2 has two control electrodes (not shown) respectively connected to a line 4 and to a column 6. Each cell 2 is represented by its equivalent capacitor. A line control circuit 8 includes, for each line 4, a line activation/deactivation block 10 having an output connected to the considered line. A column control circuit 12 includes, for each column 6, a column control block 14 having an output terminal O connected to the considered column 6. Each block 14 includes an input terminal E. Circuit 12 also includes a storage register 16 connected to receive column control signals (COL) from means not shown. Register 16 includes as many Q outputs as there are blocks 14. Each Q output is coupled to input terminal E of a block 14 via a logic switch 18. All logic switches 18 (here, AND gates) are controlled by the same enable signal VAL, provided by means not shown. Circuits 8 and 12 are conventionally integrated on the same semiconductor chip of a control circuit.
Conventionally, the cells of a plasma screen are activated line by line. The non-activated lines are submitted to a quiescent voltage (for example, 150 V). The activated line is brought to an activation voltage (for example, 0 V), the columns being at a deactivation voltage GND (0 V). Then, to activate selected cells in the activated line, the corresponding columns are brought from deactivation voltage GND to an activation voltage VPP (80 V) for a predetermined duration. Thus, the columns corresponding to the selected cells are each submitted to a voltage square pulse of the same amplitude and of same amplitude and the same duration. The columns corresponding to the unselected cells of the activated line are maintained at voltage OND. Thus, the cells to be activated are submitted, during the voltage square pulse, to a column-line voltage equal to VPP-GND (80 V). All non-activated lines are at the quiescent voltage (150 V). The column voltage being either 0 V or 80 V, the cells of the non-activated lines are reverse biased and are not submitted to a voltage capable of starting the gas ionization.
FIG. 2 shows a conventional column control block 14. An N-type MOS transistor T1 has its drain connected to voltage VPP and its source connected to output terminal O. An N-type MOS transistor T2 has its drain connected to output terminal O and its source connected to voltage GND. A zener diode 20 is connected by its cathode to the gate of transistor T1 and by its anode to the source of transistor T1. A P-type MOS transistor T3 has its source connected to voltage VPP and its drain connected to the gate of transistor T1. An N-type MOS transistor T4 has its drain connected to the gate of transistor T1 and its source connected to ground (GND). P-type MOS transistors T5, T6 have their sources connected to voltage VPP. The gate of transistor T5 is connected to the drain of transistor T6 and the gate of transistor T6 is connected to the drain of transistor T5. An N-type MOS transistor T7 has its source connected to ground and its drain connected to the drain of transistor T5. An N-type MOS transistor T8 has its source connected to ground and its drain connected to the drain of transistor T6. The gate of transistor T3 is connected to the drain of transistor T6. The gates of transistors T2, T4, and T7 are connected to input terminal E via an inverter 22. The gate of transistor T8 is connected to the output of inverter 22 via an inverter 24. Output terminal O is connected to a column 6. In FIG. 2, a capacitor C2 connects column 6 to ground. Capacitor C2 is the equivalent capacitor of column 6. It is mainly formed of a first component corresponding to the capacitance between the selected column and the screen lines, and of a second component corresponding to the capacitance between the selected column and its neighboring lines. Capacitance C2 does not have a constant value, as will be seen hereafter.
Block 14 is provided to submit column 6 to a voltage square pulse when its input E receives a logic “1” (for example, a voltage VDD equal to 5 V), then a logic “0” (0 V). When input E receives a logic “1”, block 14 charges capacitor C2 to a voltage substantially equal to VPP (which will be called VPP for simplicity). When input E receives a logic “0”, block 14 discharges capacitor C2 and the voltage of column 6 switches from VPP to GND. The value of the capacitor C2 of a column 6 depends on the voltages to which the neighboring columns located on either side of this column 6 are submitted. Thus, when a column 6 is submitted to the voltage square pulse, the capacitor C2 of this column has a maximum value if none of the two neighboring columns is submitted to a voltage square pulse. Capacitor C2 has a minimum value if the two neighboring columns are submitted to a voltage square pulse, and a value substantially equal to half of the sum of the maximum and minimum values, which will be called hereafter the median value, if only one of the neighboring columns is also submitted to a voltage square pulse.
It is important for the proper operation of a plasma screen that the rise and fall times of the voltage square pulse provided to each selected column be smaller than a predetermined maximum duration. The maximum rise time of the voltage square pulse may be different from the maximum fall time of the voltage square pulse. For simplicity, they will be assumed to be equal. The maximum admissible rise/fall duration of the voltage square pulse and the different values of capacitance C2 are features of each type of plasma screen. For a given type of screen, blocks 14 are provided, to each provide (and receive) a predetermined current enabling charging (and discharging) the capacitor C2 with the maximum capacitance of he considered screen type in a time shorter than the maximum admissible rise/fall duration of the voltage square pulse for this type of screen. Especially, transistors T1 and T2 are sized to conduct this predetermined current when on.
However, when capacitance C2 has its median value or its minimum value, the rise/fall durations of the voltage square pulse are shorter than the rise/fall durations observed for the maximum capacitance C2. Accordingly, block 14 provides or absorbs the preceding predetermined current for a variable duration depending on the selection of the neighboring columns. As a result, each block 14 introduces, when capacitance C2 has its minimum value, intense variations in the current consumption for very short durations, which may create electromagnetic disturbances on the power supply and the ground of the control circuit, which is not desirable.
Further, a control circuit having its blocks 14 sized to control a screen of a specific type may not be usable to control another type of screen.